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Text File  |  1992-06-18  |  922 b   |  52 lines  |  [TEXT/MPS ]
  1. module system;
  2.  
  3.     wire     [31: 0]a;
  4.     wire     [31: 0]d;
  5.     wire             start;
  6.     wire             ack;
  7.     wire             rw;
  8.     wire             near;
  9.     reg                 reset;
  10.     reg                 clock;
  11.     
  12.     wire     [ 9: 0]ma;
  13.     wire             w;
  14.     wire             mras;
  15.     wire             vras;
  16.     wire             cas;
  17.     
  18.     
  19.     cpu1    cpu(.reset(reset),.clock(clock),.a(a),.d(d),.start(start),.rw(rw),.ack(ack),.near(near));
  20.     
  21.     cntrl    cnt(.reset(reset),.clock(clock),.a(a),.start(start),.rw(rw),.ack(ack), .near(near), .vras(vras), .mras(mras), .cas(cas), .ma(ma),.w(w));
  22.     
  23.     memory    m(.d(d),.mras(mras), .cas(cas), .ma(ma),.w(w));
  24.     
  25.     video    vid(.d(d),.vras(vras), .cas(cas), .ma(ma),.w(w));
  26.         
  27.     always 
  28.         #5 clock = ~clock;
  29.     
  30.     initial 
  31.         $gr_waves("reset",reset,
  32.                   "clock",clock,
  33.                   "a",a,
  34.                   "d",d,
  35.                   "start",start,
  36.                   "ack",ack,
  37.                   "rw",rw,
  38.                   "mras",mras,
  39.                   "vras",vras,
  40.                   "cas",cas,
  41.                   "ma",ma,
  42.                   "w",w
  43.                             );
  44.     
  45.     initial begin
  46.         reset = 0;
  47.         clock = 0;
  48.         #100;
  49.         reset = 1;
  50.     end
  51.  
  52. endmodule